In mobile radio transmission/reception devices, the hardware architecture takes on an important role, since it influences critical parameters such as power consumption and data processing speed to a great extent. Modem mobile radio transceivers always comprise a microprocessor, usually a digital signal processor (DSP), which plays a central role in data processing tasks, such as equalization and channel decoding.
In principle, it is possible for all of the equalization of the received data to be performed solely using a DSP operated with appropriate software. However, this solution, which is the easiest imaginable in terms of hardware architecture, has a series of drawbacks. In particular, it is necessary to use very powerful and hence expensive DSPs in order to ensure the required signal processing speed. Furthermore, such DSPs have a power consumption which is unacceptably high for mobile stations.
To reduce the power consumption and the MIPS (Million Instructions Per Second) load in the microprocessor or DSP, processor or DSP tasks are transferred to specific hardware peripherals. By way of example, it is already known practice to provide support for the execution of the ACD (Add Compare Select) step in Viterbi equalization or Viterbi decoding using suitable hardware data paths. These calculate particular, ever recurrent computation tasks and thus relieve the burden on the DSP. One drawback, however, is that the use of such hardware peripherals greatly restricts the flexibility of the data processing. The attendant difficulties become more acute in higher generation mobile radio systems, which require flexible service and data administration management.
In data processor technology, it is generally known practice to provide support for user programmable processors by providing task-specific coprocessors. The coprocessor undertakes the execution of complicated operations which would be a great burden on the processor. The best known types are arithmetic coprocessors for performing the four basic types of computation and possibly transcendental functions, and also graphics coprocessors. In this case, data interchange between the processor and the coprocessor takes place via a coprocessor interface.
European patent specification EP 0 789 882 B1 describes a multimedia processor architecture in which a user programmable processor has a plurality of task-specific processors with a high power density connected in parallel with it. The task-specific processors are either nonprogrammable or have a low level of programmability, i.e. their behavior can be altered by prescribing parameters. The low level of programmability allows these processors to be used in respective different algorithms, where the same basic functions are performed, but with different parameter values. Parameter values for a particular algorithm are typically updated—i.e. the task-specific processor is configured—at a much lower speed than the data processing speed. Parameters can be reloaded using a separate bus.